| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 86 | A Novel Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement Authors:B. NAGARJUN SINGH, K. DEEPIKA |
0461-0467 |
Download | |
| IJVDCS 87 | Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Authors:G. SUNITHA, P. MURALI KRISHNA |
0468-0471 |
Download | |
| IJVDCS 88 | Designing of Multi-Operand Decimal/Binary Adder for Filter/Fast Addition Architectures Authors:VARIGALA SRAVIKA, D. SUNIL SURESH |
0472-0476 |
Download | |
| IJVDCS 89 | Implementation of Extend Orthogonal Latin Square Codes for Error Correction Authors:M. VENU, S.MOUNIKA, B. NAGARJUN SINGH |
0477-0481 |
Download | |
| IJVDCS 90 | Design of One-Step MSD Optical Adder with Restricted Input Symbols Authors:KOLIPAKA SWAPNA, S. RANJITH KUMAR |
0482-0487 |
Download | |
| IJVDCS 91 | Design Implantation of Efficient Binary Comparators for Nano-Scale Level Quantum-DOT Cellular Automata Authors:M. VENU, Y.SATYAVATHI, B. NAGARJUN SINGH |
0488-0495 |
Download | |
| IJVDCS 92 | Design and Implementation Floating-Point Multiplier Design using Combined Booth and Dadda Algorithms Authors:K. NAGALAXMI, B. VASU NAIK |
0496-0499 |
Download | |
| IJVDCS 93 | Design of 128-Bit Comparator High Speed 4-Bit Architecture Authors:PAIDALA SUNANDHA, D. SUNIL SURESH |
0500-0503 |
Download | |
| IJVDCS 94 | Design and Analysis of Low Power Pulse Triggered Flip-Flop Based on Single Feed-Through Scheme Authors:MOHMAD YASMEEN, B. VASU NAIK |
0504-0508 |
Download | |
| IJVDCS 95 | Design and Implementation of Single Phase Clock Distribution using Prescaler Authors:GADUGONI SUSMITHA, D. SUNIL SURESH |
0509-0513 |
Download | |
